The present invention relates generally to semiconductor integrated circuit (IC) memory chips or devices, and more particularly to serial erasable programmable memory devices such as electrically erasable (alterable) programmable read only memories (serial EEPROMs). EEPROM devices generally have the advantage that data may be written and rapidly erased electrically many times over, to permit a user to modify stored data at will while the device is in circuit.
ROM devices are permanently mask-programmed at the factory so that no subsequent data modification is permitted. Originally, programmable ROMs (PROMs) employed fusible links in which data is stored according to the condition of the fuses at intersections of the memory array, i.e., the condition of whether or not a fuse is blown. Such PROM devices are programmable only once (that is, are non-erasable) since a blown fuse is not reparable.
EPROM devices require exposure of the unhoused structure to ultraviolet (UV) light to change the electrical characteristics of a charged element in order to obtain erasure. Typically, the EPROM is housed in a windowed package (e.g., a ceramic package having a quartz window to expose the silicon), although a more recent version dubbed as "one time programmable" (OTP) is packaged in plastic without a window. As the name indicates, the windowless variety can be programmed only once. The usual windowed EPROM is reprogrammable after removal from its in-system circuit, by exposing the device to UV for a sufficient period of time (several hours) to assure complete erasure, then electrically reprogramming and reinstalling it in the circuit.
Since EEPROM devices are rapidly erasable in circuit, they are the memory devices of choice in applications where in-system changes of stored data and/or relatively fast data changes may be required. Serial EEPROMs are nonvolatile memories that provide small footprint and board space as required in cellular phone applications; byte level erase, write and read of data as needed in television tuner applications; low voltage and current for hand held battery applications such as vehicle keyless entry transmitters; and multiple nonvolatile functions such as remote controls for VCRs. Although the following list is not exhaustive, other applications of serial EEPROM devices include, in the consumer market, CD players, cameras, radios and remote controls; in the automotive market, airbags, anti-lock brakes, odometers and radios; in the office automation market, printers, copiers and personal computers; in the telecommunications market, cordless and full feature phones, fax machines, modems, pagers and satellite receivers: and in the industrial market, bar code readers, POS terminals, smart cards, lock boxes, garage door openers and test measurement equipment.
In the EEPROM structure, a pair of polysilicon gates are separated by a silicon dioxide layer. The oxide also extends below the lower gate to separate it from underlying p-type silicon substrate in which a channel may be established between implanted heavily doped n-type source and drain regions. The oxide thickness between the lower gate and the silicon typically ranges up to about 100 angstroms, which is considerably less than the gate oxide thickness used for EPROM structures.
In operation of an EEPROM, a voltage of suitable magnitude applied across the very thin gate oxide layer induces tunneling of electrons from the substrate to the lower gate. A logical 1 is stored (written) when a write voltage is applied to the upper gate, thus inducing a charge on the lower gate that prevents a channel from forming during a read operation. A reversal of the write voltage causes erasure.
It is imperative that the power supply of the EEPROM device be maintained at a sufficiently high voltage level to assure an internal programming voltage adequate to write the memory completely. The need becomes more acute where the device is designed to operate at low voltage, such as in battery-operated CMOS (complementary metal-oxide-silicon) design applications at less than 6 volts and even below 2 volts. The EEPROM may be written to at any time, and if the power supply is unregulated the data may be only partially written. The non-electrically erasable EPROM does not face this problem, because it is programmed with a 12 volt supply level.
The need for constant monitoring of the supply voltage to the EEPROM chip (V.sub.DD) has led to the inclusion of a brownout detector in circuit to detect voltage spikes and consequent loss or corruption of data. If the supply voltage drops to a level below that required to write the EEPROM, even if only momentary, the brownout detector detects this deficiency and aborts any pending write operation. Consequently, there is no chance of data corruption through incomplete writes. However, among other problems associated with them, brownout detectors implemented in MOS technology draw power--at a level of consumption that may not be acceptable in battery applications.
Heretofore, the typical solution to this problem has been to use non-brownout detect circuits to control the semiconductor chip, which can aggravate the problem of a collapsing V.sub.DD (i.e., a weak battery). A non-brownout detect circuit, or what is typically called a power-on-reset (POR) circuit, holds the device in reset while the power supply is slewing up to its final value. Once the supply voltage is sufficiently high, the POR circuit will enable the device and turn itself off. Thereafter, if any supply spikes occur the POR circuit is unable to detect them, since it is turned off, with the result that the device may behave incorrectly.
Accordingly, it is a principal object of the present invention to provide improvements in power management of erasable programmable memory arrays, and especially for serial EEPROM devices.